1. Field of the Invention
This invention relates to an apparatus for interfacing between a peripheral device and a host processor. The invented cache memory and pre-processor operates in either an acquisition mode, where it appears to be a memory dedicated to the peripheral, or in a retrieval mode, where it appears to be a memory dedicated to the host processor.
2. Description of the Prior Art
Certain peripheral devices, such as a laser doppler velocimeter, generate data which are not time continuous, and the regularity of the occurrence of new data are not known a priori. Certain peripheral devices of this nature can generate an average data rate in 10.degree. sec.sup.-1 to 10.sup.4 sec.sup.-1 range, with intermittent data burst as high 10.sup.6 sec.sup.-1. However, the host processor which acquires the data and calculates mean and standard deviation values, can be throughput limited to approximately 3.times.10.sup.3 samples per second, given an interrupt driven routine dedicated to servicing the peripheral and storing data in sequential memory locations. It is therefore obvious that there is a general incompatability between the peripheral device and the memory mapped host processor system, with the result being lost data. Certain prior art systems have attempted to resolve these incompatabilities. Certain systems used a buffer and processor combination; however, such systems must acquire data and perform calculations one data element at a time. These calculations are made in real time, as the data is being produced, and since the software calculations are slow, data can be lost. Alternatively, the peripheral host processor can address a dual port RAM. However, a dual port RAM would not be useful if 16 -bit words were acquired from the peripheral and only 8-bit words could be read by the host processor's data bus.